Ph.D. Researcher, Norwegian University of Science and Technology (NTNU)
PCIM EUROPE 2021 - 3. WINNER OF YOUNG ENGINEER AWARD An adaptive SiC MOSFET gate driver
This article presents a novel current source gate driver for SiC MOSFETs improving controllability of turn-on/off delays, di/dt and dv/dt compared to conventional totem-pole voltage source gate drivers.
Silicon Carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) – a wide-bandgap (WBG) semiconductor – exhibit several advantages in high-voltage and high-power applications. This is mainly due to their higher maximum operating temperature, higher blocking voltages, lower power losses and faster switching speeds that enable operation at higher switching frequencies compared to Silicon-based counterparts. With increasing switching speeds enabled by SiC power MOSFETs, fast rise and fall times during switching transients are desirable to reduce the anticipated hard-switching losses.
However, the achievable high di/dt and dv/dt impose challenges on the optimal electrical performance of WBG-converters. High di/dt can induce oscillations in drain-source voltage vDS and gate-source voltage vgs due to parasitic inductances. These oscillations can lead to overvoltages, electromagnetic interference (EMI) and radiofrequency (RF) emissions, as well as increased switching loss. High dv/dt can – additionally to EMI and RF emissions – induce voltage spikes in vgs due to Miller current injection in bridge circuits (crosstalk), cause overvoltages in connected equipment (e.g. motor terminals) due to the transmission line effect as well as being potentially hazardous to insulation materials and motor bearings1-3.
Thus, a gate driver which can control the di/dt, dv/dt and turn-on/off delay times can be beneficial, and even adapt the power electronic system characteristics (i.e. di/dt, dv/dt and turn-on/off delay) to changing applications or environment without doing changes to the hardware.
The proposed current source gate driver – with a simplified schematic shown in Fig. 1 – works by injecting/extracting charge to/from the gate (G-Sk) in two intervals by charging three different inductors, LH, LM and LL using the switches T1-T4 and Taux.
The first interval controls the turn-on/off delay as well as the di/dt, while the second interval controls the dv/dt. Considering the turn-on instant, the magnitude of the first current pulse is generated by charging LM through the switches T1 and T4 in a pre-charging interval, starting at t0 (Fig. 2). The turn-on/off delay time can be regulated by sizing the pre-charge interval, as the current path from O to Sk via LL and the path from O to Sk via the gate of the device under test (DUT), cause a current divider.
The current divider lets a small current into the gate prior the actual turn-on instant (ig(pre)), causing a slight increase in vgs, reducing the turn-on delay. The DUT is turned on by releasing the first current pulse into the gate at t1 and the di/dt can be regulated by the magnitude of the first current pulse. After first turn-on, a second current level is prepared by charging LH and LL via Taux during the auxiliary-charging interval, starting at t2. The second current level is then injected or extracted from the gate at t3 by turning T3 on while turning Taux off. For example, if an increase in the dvDS/dt is desirable, a high valued second current can be injected when vgs reach the Miller plateau. This is when vDS starts to fall during turn-on, and a high dvDS/dt can reduce the turn-on switching loss. Conversely, if a lower dvDS/dt is desirable – e.g. for EMI or safety reasons – a lower valued second current can be injected at the Miller plateau. The resolution of the current intervals is approximately 5ns with FPGA generated switching patterns.
The driver can for example be utilized in a closed loop slew rate control scheme (Fig. 3) deploying a PI-controller for the dvDS/dt.
In Fig. 4, simulation results showing a closed loop control scheme is used to control the voltage slew rate during turn-off. It can be observed how the driver allows for flexibility choosing between high dv/dt – yielding lower switching losses but causing more severe oscillations in vDS – and low dv/dt – increasing the switching losses.
The functionality of the proposed driver is verified experimentally on a passive capacitive load C_L, imitating the input capacitance CL=Ciss≈200nF of the 3.3kV/750A SiC MOSFET half-bridge module. Experimental waveforms showing different auxiliary current injection times and how it affects the voltage across the load can be seen in Fig. 5. It can clearly be observed how manipulating the second current injection – achieved by only varying the timing intervals of the driver – affects the voltage across the capacitive load depending on the current magnitude.
1.) B. Liu, R. Ren, Z. Zhang, B. Guo, F. Wang, and D. Costinett, “Impacts of high frequency, high di/dt, dv/dt environment on sensing quality of GaN based converters and their mitigation,” CPSS Trans. Power Electron. Appl., vol. 3, no. 4, pp. 301–312, Dec. 2018, doi: 10.24295/CPSSTPEA.2018.00030.
2.) M. Pastura, S. Nuzzo, M. Kohler, and D. Barater, “Dv/Dt Filtering Techniques for Electric Drives: Review and Challenges,” in IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society, Oct. 2019, vol. 1, pp. 7088–7093. doi: 10.1109/IECON.2019.8926663.
3.) G. Skibinski, D. Leggate, and R. Kerkman, “Cable characteristics and their influence on motor over-voltages,” in Proceedings of APEC 97 - Applied Power Electronics Conference, Feb. 1997, vol. 1, pp. 114–121 vol.1. doi: 10.1109/APEC.1997.581441.