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Dr. Christina DiMarino

Dr. Christina DiMarino

Assistant Professor, Center for Power Electronics Systems (CPES), Virginia Tech

MEDIUM-VOLTAGE PACKAGING Breaking the power density limits for medium-voltage power modules

Author / Editor: Dr. Christina DiMarino / Jochen Schwab

Wide-bandgap (WBG) power devices with voltage ratings exceeding 10 kV have the potential to revolutionize medium- and high-voltage systems due to their simultaneous high blocking voltage, fast switching speed, and good controllability. These features can drastically reduce the size and complexity of power electronics systems.

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PCB-integrated bus bar and gate driver for 10 kV SiC MOSFET half-bridge module, with high-speed short circuit and overload protection.
PCB-integrated bus bar and gate driver for 10 kV SiC MOSFET half-bridge module, with high-speed short circuit and overload protection.
(Source: Dr. Christina DiMarino)

Application areas for these emerging switches include renewable energy, industrial motor drives, rail traction, electric power grid, defense, and aerospace. However, present power module packages are limiting the performance of these unique medium-voltage devices. Asymmetric device layout and bulky system interfaces cause high commutation inductance, limiting switching speed and increasing losses.

Conventional manufacturing techniques and materials limit operating temperatures and have high thermal resistance, restricting current ratings. The proposed package seeks to mitigate these issues by eliminating the wire bond interconnects, employing silver sintering, and codesigning the power module with the laminate bus bar and integrated gate driver. These approaches enable faster switching speed, higher operating temperatures, improved reliability, higher power density, and streamlined integration.

Project summary

A high-density package for 10 kV silicon carbide (SiC) power MOSFETs has been proposed. The scalability, system integration, switching, and reliability of the proposed 10 kV SiC power module has been evaluated and verified. To demonstrate the current scalability, variants with 2 SiC MOSFET dies and 6 SiC MOSFET dies were developed and tested. Versions for 6.5 kV devices were also evaluated to demonstrate the voltage scalability.

10 kV SiC MOSFET half-bridge power module (69mm x 62mm x 16mm).
10 kV SiC MOSFET half-bridge power module (69mm x 62mm x 16mm).
(Source: Dr. Christina DiMarino)

The module and bus bar were codesigned to achieve a compact interface that improves the inherent tradeoff between high voltage and high density. The interface utilizes PCB embedded guard rings around enclosed spring-pin terminals to achieve a voltage-scalable, compact interface between the module, the gate driver, and the bus bar. Partial discharge testing was conducted to verify the insulation performance. The developed interface achieves a partial discharge inception voltage of 11.6 kV rms with only 6 mm spacing between the high voltage terminals.

The switching tests were performed up to 6 kV. No external gate resistance was used, resulting in a fast switching speed of 140 V/ns. Due to the low-inductance design, negligible voltage overshoot and ringing were observed.

PCB-integrated bus bar and gate driver for 10 kV SiC MOSFET half-bridge module, with high-speed short circuit and overload protection.
PCB-integrated bus bar and gate driver for 10 kV SiC MOSFET half-bridge module, with high-speed short circuit and overload protection.
(Source: Dr. Christina DiMarino)

The module uses two sintered direct bonded aluminum substrates instead of a baseplate. This unique design allows for 50 % higher partial discharge inception voltage. Thermal cycling from -40°C to 200°C was performed on the sintered substrates, which are bonded using low-pressure silver sintering. Cross-sections were cut and imaged to monitor the sintered silver bond. No failures were observed after 500 thermal cycles. Thermomechanical simulations suggest that the sintered substrates have higher reliability compared to traditional substrate-to-baseplate designs.

Impact

This work seeks to improve the tradeoff between power density and high voltage. The compact interface, large-area silver sintering, and wire-bond-less and current-scalable module layout provide high voltage operation and high density formfactor without compromising long term reliability, electrical insulation, or device performance. The proposed system is scalable in terms of both voltage and current rating, and demonstrates techniques that are viable for reducing module and converter footprints – a need which is present in a wide range of applications.

(ID:47111107)

About the author

Dr. Christina DiMarino

Dr. Christina DiMarino

Assistant Professor, Center for Power Electronics Systems (CPES), Virginia Tech