PFC CONVERTER Control loops and startup for PFC converters

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The power factoring correcting (PFC) converter does not often get a lot of love or attention. For low and medium power levels (let’s say up to 1000W or so), a suitable reference design is often copied and then little time is budgeted for testing and proving it. Yet this part of an AC-DC power supply unit (PSU), is the base for the rest of the design.

Power factor needs to be corrected for nearly all PSU’s that connect to AC power distribution networks, and I myself have been guilty of not paying enough attention to the startup of the PFC stage or its control loop. These two things are interdependent, and neglecting them cost me time - and money!

A short time ago, I developed a three-stage, 200W (input power) PSU. The first stage was a quasi-resonant boost PFC, and I was guilty of not planning much time to test the prototypes. I was excited to try out the following stages, which were topologies I hadn’t worked with very much before. But my client and I found several operating areas where the PFC part of the system would not start up. After some testing, I found this:

I should not have been surprised, since just about every time I work with a new self-starting AC-DC or high-voltage DC (HVDC) system I run into this kind of “hiccup” or “motorboating”. This kind of infinite loop can ruin your day (or week) when there’s a race condition between the draining of the capacitor(s) on the VCC pin of the control IC and the charging of those capacitors by an auxiliary winding on the transformer or the inductor, depending upon the topology. Usually this winding operates as a flyback converter, and that was the case for my circuit. In Figure 1, the switching pulls VCC down too quickly, the flyback winding doesn’t start pumping current into VCC fast enough, and the control IC goes into under-voltage lockout (UVLO). Then the whole process repeats. Quasi-resonant controllers are usually variable frequency, making frequency hard to predict during startup. I spent a lot of time changing the large signal aspects of the circuit - reducing the PFC converter’s output capacitance, increasing the boost inductance, increasing the VCC pin capacitance – but it wasn’t until I noticed that the control IC’s evaluation board had a Type II control loop compensation that I considered the small signal aspects. I had followed the IC datasheet and placed a single capacitor, Type I compensation. As it turned out, that made the response of the system either too slow (hiccupping) or nearly unstable (barely any phase margin). Figure 2 shows about one second’s worth of oscillation in the output voltage after a successful startup with a faster but low phase margin control loop.

Few PFC controllers provide a small-signal model of their power stage, and although their low frequency poles are easy to predict, their DC gains are not. What I did for this circuit, and what I always do now is to get the system up and running and then take Bode plots of the power stage (the control-to-output transfer function) and the complete loop. I then use a two-capacitor one-resistor Type II compensation to make the loop as fast as possible and with excellent phase margin. A PFC’s control loop can’t be made very fast or it will stop correcting power factor, but there’s a very real difference between a loop bandwidth of 0.1 Hz and a loop with a bandwidth of 20 Hz. It can easily be the difference between actually starting up and being stuck hiccupping as seen in Figure 1. There’s also an important difference between 10° of phase margin and 70°, as seen in Figure 3, below.

You could argue that the downstream converter stages should reject the slow oscillation of Figure 2. They should also reject the oscillations caused by any load transients. But I would counter that the PFC is the bedrock upon which the converter is built, and it should be as stable as possible. All it takes is some time spent at the beginning, one small resistor and one small capacitor.

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