Tools & Software Examine DDR3 memory with an oscilloscope
DDR3 memory devices can be examined with an oscilloscope. Together with a special software option for the scope, developers can perform various tests.
DDR3 was already standardized by the JEDEC consortium in 2007. The memory devices are still the first choice for many applications in industry, medical technology or automotive engineering. They are less expensive than modern memory devices, reliable, compact and have a large data volume. DDR3L (low voltage) and LPDDR3 (low power) versions are ideal for optimized power consumption.
For the DDR3 standard, memory devices with data rates from 0.8 to 2.133 GBit/s are specified. Devices require a stable power supply within the specified tolerances without coupled interference from other functional units. Developers need to control signal integrity on the fast data lines using oscilloscopes for troubleshooting. Conformance tests are also possible when commissioning a circuit with DDR3 memory. With the R&S RTO/RTP-K91 option, Rohde & Schwarz offers the option of decoding DDR3 read and write cycles, analyzing eye diagrams and performing automated conformance tests according to the DDR3, DDR3L, and DPDDR3 standards.
Eye-diagram and quality of transmission parameters
DDR3 interfaces use a parallel bus structure in which eight ground related data lines DQ 0 to DQ 7 are each coded with a differential strobe signal and transmitted as a data strobe signal (DQS) (Fig. 1). In the eye diagram of the individual DQ signals, the transmission bits refer to the rising and falling edges of the DQS clock signal. The eye diagram can be used to estimate the quality of most transmission parameters. Via the horizontal axis, the measurement engineer can, for example, read the temporal eye-opening and the jitter on the sides of the eye (bit transitions), and on the vertical axis the vertical eye-opening and the noise.
The R&S RTO and R&S RTP oscilloscopes have analysis options such as automatic eye measurements, horizontal and vertical histograms for jitter and noise analysis or masks for long-term stability tests (Fig. 2). You can use the DDR Eye Diagram function of the R&S RTO/RTP-K91 option to record several million bits and display them as eye diagrams. The function uses the edges of the DQS signal to split the DQ signal into bits for the eye diagram display. It also provides targeted analyses such as gate qualifiers or bit sequence filters. In combination with the read-write decoding function of the DDR3 option, the eye diagram for read and/or write cycles can be displayed.
With DDR3, the DQ and DQS signals are transmitted bidirectionally. To differentiate between read and write cycles, the edges of the DQ signals are phase-shifted to the DQS signal: In the read cycle, when the memory device sends data to the processor, the edges are equal in time. In the write cycle, when a processor sends data to the memory device, the DQ signal edges are offset by half a bit width (Fig. 3). The clock offset makes simple eye diagram representation and the measurement of temporal parameters more difficult. Read and write cycles are to be broken separately by specific triggering at the start of the read and write cycles. The digital trigger system of the oscilloscopes supports complex A-B-R trigger sequences (trigger events A, B and reset) and reacts to small signal changes and pulse widths below 50 ps due to the digital architecture. The different preambles for the read and write cycles (Fig. 4), for example, are interesting for triggering.
Triggering specific read and write cycles
With a pulse trigger, the user can trigger negative reading preambles that are slightly longer than one-bit width. For a DDR3 device with a data rate of 1.333 GBit/s (≈ 750 ps bit width), for example, a negative pulse trigger of greater than 1 ns makes sense. If the user wants to trigger the write cycles, it is best to use an A-B-R trigger sequence that searches for write preambles with a bit length slightly longer than one-bit width. The A trigger then serves as a pulse width trigger and should be set with negative polarity to the width of > 2 ns to match the start of write cycles. The B-trigger is set accordingly to the positive pulse width of the write preamble of > 750 ps and the R-trigger to 2 ns. If no valid B trigger event occurs after an A trigger event, the R trigger resets the trigger system to the A search.
Users can also use the R&S RTO/RTP-K19 zone trigger option to select specific read or write cycles. It can be used to define zones that must either be run through or avoided for valid triggering. When triggering on read cycles, for example, you can define a trigger zone in the DQS signal that reacts to the read preamble. Further zones in the DQS and DQS signal then target, for example, simultaneous edges.
The decoding function of the DDR3 option also recognizes the read and write cycles. Within an acquisition of DQS and DQ signals, it identifies the read and write cycles via the phase shift of the signal edges. The user simply selects the channel assignment of the DQ and DQS signals and sets the thresholds and hystereses via the Auto Threshold function (Fig. 5). The decoded signals are then available to other functions of the solution such as the DDR Eye Diagram (Fig. 6). If the user displays the signals in the Eye Stripe, the mask violations in the time signal are marked red on the time axis. A coupling with the zoom window also allows navigation between mask violations.
Automated conformance tests and the derating value
A manufacturer uses conformity tests to check whether the design complies with the specifications of the standard. This should be measured with an automated test solution that is as efficient as possible. The R&S RTO/RTP-K91 provides detailed instructions on signal contacting for automated conformance tests, configures the oscilloscope automatically, records and measures the necessary waveforms and outputs a summary of the results in a report. The option checks test objects for conformity with the standards DDR3 (JESD79-3), DDR3L (JESD79-3-1 and JESD79-3-1A.01) and LPDDR3 (JESD209-3C). It guides the user through the measurements using images and text and provides information on which signals are to be connected to which channels of the oscilloscope and which measurement signals should be visible (Fig. 7). The results are processed in such a way that the user gets a quick overview but also gets to the details quickly without having to generate a report (Fig. 8).
Depending on the actual slew rate of the DQ and DQS signals, a bonus or penalty is added to the measurement limit value via derating. The solution determines the slew rate for each setup & hold measurement on the falling and rising edges of the signals. The derating value must then be calculated by interpolating the calibration values defined in the JEDEC standard. The R&S RTO/RTP-K91 automatically performs measurements with derating. It separates the cycles from the DDR3 signal into read and write cycles. It then activates the corresponding measurements over the defined signal time, graphically prepares the results for the worst measured value and summarizes them in a report.
The JEDEC standard for DDR3
The DDR3-JEDEC standard divides the interface tests into timing tests and electrical tests. The specifications for timing tests can be used to test the temporal behavior of the individual signals. The tRPRE measurement ensures, among other things, that the reading preamble lasts longer than 90 percent of a clock cycle. The start time of the preamble is determined by the intersection of the falling edge of the strobe signal with the zero point.
Endpoint is determined by the next zero crossing of a rising edge of the strobe signal. Similar measurements are prescribed for the other signals. The option covers all specified timing tests for the DDR3 conformity test.
Differential Signals and the Electrical Test
In electrical tests, the standard requires that the properties of the individual lines (V+, V-) be investigated separately for differential signals. Only one signal is considered for these measurements. For the determination of the read and write cycles, however, the DQ and DQS signals are sometimes additionally required. For example, the DQS signal is required for the parameter VIHdiff(AC). It represents the high dynamic voltage value of the differential DQS signal, which is determined using a histogram.
The JEDEC-DDR3 specification refers to the signals directly on the DRAM device, which is why the measuring points should be contacted as close as possible to the memory device during troubleshooting and signal integrity tests. DDR3 memory devices are usually soldered to the printed circuit board or a DIMM module. With single-sided PCBs or DIMM modules, it is possible to reach the signal line via the vias (Fig. 9). If rear contacting is not possible, the user can insert an interposer for connecting the probes between the DRAM device and the DIMM. This leads to contacts of the desired signal lines to the outside.
Minimizing inductivities and capacitances
Regardless of the type of contact, the contacts must be kept as short as possible to minimize additional inductivities and capacitances. The R&S RT-ZM modular probes measure differential, ground or common-mode voltages in MultiMode mode.
If differential signals such as clock or DQS signals are to be measured, the differential inputs UP and UN as well as the ground contacts are connected to the oscilloscope. In MultiMode, the user can switch between differential and ground mode for electrical tests.
In detail: Oscilloscope family R&S RTP with 16 GHz for DDR4
For moderate data volumes, DDR3 memory chips are completely sufficient. Even DDR4 devices with more memory and clock rates up to 3.2 GHz can be measured with an oscilloscope. At the beginning of September, Rohde & Schwarz introduced the R&S RTP-K93 software option for the new R&S RTP oscilloscopes with bandwidths of 13 and 16 GHz for troubleshooting and conformity measurements on DDR4 and LPDDR4 interfaces. This makes read and write decoding with oscilloscopes possible for DDR4 as well.
Also, the user can test signal integrity with up to four DDR4 eye diagram tests or perform automated certification measurements according to the relevant JEDEC standards.
The oscilloscopes of the RTP series can be used to perform read and write decoding with an oscilloscope for DDR4. The user can also test signal integrity with up to four DDR4 eye diagram tests or measure it automatically and certified according to the relevant JEDEC standards. If the user uses the devices with up to four measurement channels, the maximum bandwidth is 8 GHz.
The oscilloscopes are suitable for the commissioning and characterization of circuits with fast digital interfaces up to data rates of 10 Gbit/s. The oscilloscopes can also be used for the characterization of circuits with fast digital interfaces up to 10 Gbit/s data rates. In addition to a function for real-time de-embedding, the instrument offers the possibility of using all trigger types up to the maximum instrument bandwidth. Also, the user has an acquisition rate of over 750,000 measurement curves/second at his disposal.
This article was previously published in German on Elektronikpraxis.
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