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Products & Applications MOSFET driver: a common cause of failure

Author / Editor: Markus Rehm * / Jochen Schwab

Reliable power supplies are a basic requirement for low failure rates of electrical appliances. This article explains typical power supply problems and how to avoid them.

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Markus Rehm at work: "Start testing your intended power supply as early as possible".
Markus Rehm at work: "Start testing your intended power supply as early as possible".
(Bild: IB Rehm)

Today, switching transistors almost always use MOSFETs. They are inexpensive and have small switching and conduction losses even with high dielectric strength. In addition, they are relatively easy to drive, and many integrated driver circuits are available. However, you have to be careful that MOSFET and driver IC fit together. Again and again, I find field failures, which are due to a bad design of switching transistor and driver.

Gallery with 6 images

Is there anything wrong with the selection of the MOSFET gate driver?

Figure 2 shows a typical circuit diagram with MOSFET M1 and gate driver IC. Also shown are the inductance L1 to be switched, the current measuring resistor R3 and the network between driver and gate to optimize switch-on and switch-off behavior (R1, D1, R2). You almost always choose a driver that costs as little as possible and can barely deliver the peak current needed for a fast gate charge.

FET A becomes low impedance between 0.5 and 1.5 V at the gate, with FET B it is between 1 and 4 V and with FET C the level is between 3 and 4.5 V. The current is then used to drive the FET. MOSFETs with a low gate threshold voltage are often praised as modern and good. Energy is saved - the voltage is even squared into the power dissipation.

Figure 3: Excerpt from various MOSFET data sheets.
Figure 3: Excerpt from various MOSFET data sheets.
(Bild: Markus Rehm)

Of course, this gate voltage is not sufficient for a good switch-on operation. In order to achieve a low switch-on resistance (Drain Source ON resistance, RDSon), a considerably higher gate voltage must be applied, e.g. 10 V. In order to control the MOSFET with high impedance, i.e. to switch it off, the gate voltage must be permanently and significantly below the threshold voltage. The circuit diagram shows that the driver pulls to "low". But what does "low" mean? Clear answer, "low" should be zero Volt, or at least almost zero Volt.

Figure 4: Excerpt of various gate driver IC data sheets
Figure 4: Excerpt of various gate driver IC data sheets
(Bild: Markus Rehm)

Let's take a closer look. Figure 4 shows an example of the corresponding data sheet extracts from two different gate driver ICs. With driver, A "low" means 1.5 V in the worst-case - hard to believe but true! This would be suitable for driving FET C, but with the other two FETs A and B, the switching transistor does not lock properly in the off state!

As I said, this is in the worst case, which is so rare that it probably doesn't occur during development. Only after mass production will these unfavorable combinations occur and lead to "inexplicable" failures, if you are very lucky already in the final test, but mostly only with the customer in his device.

Driver B would be much better suited, since "low" means max. 35 mV. I don't need to mention that this type is much more expensive. It is your decision whether these additional costs justify a higher reliability. Many power supply manufacturers have to tickle out the last cent and of course, decide - for the cheaper version! After all, nothing broke during the endurance test.

Does the MOSFET gate driver have any influence in the case of disturbances?

Interferences occurring in the device or field can, for example, bring additional charge to the gate via the parasitic mill capacity (from drain to source). This can cause the switching transistor to switch on undesirably and cause a bang. Therefore it is immensely important that the driver keeps the gate really low impedance!

Because some datasheets today are "glossed over" for market strategic reasons or important properties are unclearly presented, one could also test the immunity oneself. Simply feed some current directly into the gate via a resistor during operation and measure the gate voltage when it reaches the critical threshold voltage. Then you know how much coupled interference current the power supply can withstand.

Figure 5: An effective improvement is achieved with a resistance from gate to source.
Figure 5: An effective improvement is achieved with a resistance from gate to source.
(Source: Markus Rehm)

An effective improvement is achieved with a resistance from gate to source (Rgs), as shown in Figure 5. My boss would have pulled my ears earlier if I had forgotten such a resistance.

Unfortunately, I see in many failures that this gate-source resistor is missing. Many developers think that a modern driver IC is enough. Sure, even without this resistor the power supply works on the lab bench and during the endurance test. In addition, it is not shown in most application notes. The failures only come when they hurt - at the customer in the field. The customer is then accused of treating his power supplies badly, extensive endurance tests have been carried out and there have been no failures at all.

It should also be mentioned that this gate-source resistor is usually very easy to install. No matter if SMD or through-hole type, between gate and source there is always a place for a 0603 resistor. The question then would be, which resistor value should it be? In general: 47 kΩ are better than nothing, but 22 kΩ or even 10 kΩ should be. That, of course, depends on the used driver and MOSFET and also the layout plays an important role.

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Many people think that a thick line from the gate to the driver is the most important because the gate current is large and short. But the current always flows in a circle, i.e. when switching off via the driver ground, further through the shunt R3 and to the source! This area should be small, the total length as short as possible and no vias should be used. This is good for immunity and emission.

It should also be mentioned that "modern" MOSFETs are not only optimized for a low gate threshold voltage, but also for a small gate-source capacitance. Both reduce driver losses but degrade immunity. Therefore a capacitor Cgs (approx. 1 nF, not shown) could be used in parallel to Rgs. Sometimes you can also see a Zener diode from gate to source, e.g. 15 V, to avoid dangerous overvoltages.

The driver has to supply the necessary current through the additional Rgs (and possibly Cgs) and this increases the power losses. In principle, the following applies to all circuit parts: either high impedance and susceptible to interference or low impedance and high loss.

Figure 6: The green dotted box shows the output stage of the gate driver IC as complementary output stage. The red arrow symbolises the inrush current in the top FET, the blue arrow the breaking current in the bottom FET.
Figure 6: The green dotted box shows the output stage of the gate driver IC as complementary output stage. The red arrow symbolises the inrush current in the top FET, the blue arrow the breaking current in the bottom FET.
(Bild: Markus Rehm)

Is the MOSFET driver really always on or off?

Figure 6 shows the output stage of the gate driver, which basically consists of two transistors. The upper transistor (Top-FET Q1) pulls the output to high to turn on the FET M1, the lower transistor (Bottom-FET Q2) pulls to low to turn off the FET M1. Sure thing - where's the problem?

Ideally, there should be only two states, either "Q1on and Q2off", then the FET M1 is on, or "Q1 off and Q1 on" and then the FET M1 is off. In reality, this is not possible. Both transistors must not conduct simultaneously, otherwise, there is a "hot branch", i.e. a short circuit across the supply voltage VCC through Q1 and Q2. So there are always switching points where the driver output is high-impedance!

In the datasheets of the drivers, this is unfortunately mostly not well specified. Hints are given by "delay time", "rise time" and "fall time". And then the information is almost always at 25 °C, but which IC is operated at this temperature?

Let's take an example with a switching frequency of 100 kHz and a switching time of 100 ns each. This would result in a high-impedance state of 200 ns during 10 µs, which means 2% of the period! Again, only a resistor from gate to source helps to minimize the risk that the switching transistor does not accidentally switch on at the wrong time due to a disturbance.

If there is not only one switching transistor, but two, then the driving topic is even more critical. And if a switching transistor is floating in a half-bridge, i.e. has no fixed reference at the source, then correct measurement with a potential-free probe is also difficult.

Are development errors detectable in the endurance test?

Many of my customers believe that they find development errors through intensive endurance tests in the temperature cabinet with various load cycles and on-off profiles. Unfortunately, this is not the case.

If an "inexplicable" failure occurs during the endurance test, it is assumed that the test was too hard and that this does not correspond to the real case. One is already finished with the development, the necessary approvals are finally there and the brochures are printed. Nobody dares to raise their hand and order a further investigation, let alone a redesign.

In addition, it is usually the case that such failures only occur after years in the field, due to disturbances in the environment, when the components age or due to component tolerances.

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Finally, an interesting case study

In a large production plant, there were power supply failures, very rare, but the consequence was very expensive because then everything stood still and it took a long time until the production ran properly again. During the failures the switching transistor was broken, the fuse was open and partly also the gate driver IC or the shunt resistor was blown up, once also a conductor track melted.

My analysis showed that the customized power supply was not so bad (for us Swabians this means good). To be honest, I didn't find a development bug, which is very rare and I couldn't reproduce a bug either. However, I noticed that the above mentioned "breaking current loop" was a bit long, the area was large and there were even two vias. Perhaps this was where the interference emissions from the production plant were captured?

In my desperation, I complained about that and recommended installing a resistor from Gate to Source. I didn't have any good arguments, but I excluded everything else. The power supply manufacturer was angry because he had to realize the "totally unnecessary change". First by soldering the SMD resistor by hand and then a small layout redesign. A few years later I learned that there were no more failures in the following years.

In this way you avoid failures of the switching transistor and driver circuit:

  • There are different voltage thresholds of driver ICs and MOSFET gates. They have to fit together, read the datasheets for details and study the small print!
  • High-impedance times are always present at the gate and dangerous because disturbances can trigger the switching transistor. Therefore, always install a resistor from the gate to source very close (e.g. 4.7 to 22 kΩ).
  • The layout is also important: Record current loops for switching on and off in the circuit diagram and track them on the circuit board, do not stretch large areas, avoid vias. This avoids additional impedances in the control circuit and reduces susceptibility to interference.
  • The instructions also apply if the driver stage is set up discreetly.

Finally, an important tip: Many gate drivers are already built into SMPS controller ICs. This greatly simplifies the development of switching power supplies. When selecting the controller, take a close look at the internal driver. It needs a lot of semiconductor space and it costs money. That's why savings are often made there. Leave the fingers of cheap ICs where the driver is insufficiently specified. Invest a little more in a good gate driver and save the much higher costs caused by field returns. Also, you can sleep much better at night!

This article was first published in German by Elektronikpraxis.

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* Prof. Markus Rehm has been teaching industrial and power electronics at the Furtwangen University of Applied Sciences since 2008, where he was appointed honorary professor in 2019. Since 2012 he has given more than 30 lectures at national and international congresses and since 2017 he has given one-day seminars on reliable power supplies on behalf of ELEKTRONIKPRAXIS, Vogel Communications Group.