SILICON CARBIDE MOSFETS Parasitic turn-on of SiC MOSFETs – Turning a bug into a feature
Many publications have already dealt with the unwanted parasitic turn-on (PTO) of semiconductor devices and how to get rid of it. But in the same-titled paper, which was awarded with the Young Engineer Award 2020, it was shown that high power applications may even benefit from a small PTO.
In recent years, wide bandgap devices like SiC MOSFETs aim to replace Si IGBT in many applications. SiC MOSFETs show many advantages, like the absence of tail currents during turn-off or the reverse conduction, which can be used to replace external freewheeling diodes. But some challenges remain. Depending on various MOSFET parameters like threshold voltage and the values of the MOSFET capacitances, the phenomenon of parasitic turn-on may occur.
When the SiC MOSFET of one phase turns on, the Drain-Source voltage (vds) passes over from this MOSFET to the complementary MOSFET. In the latter, the positive (dvds/dt) introduces a capacitive current over the Gate-Drain capacitance (Cgd), which charges the Gate-Source capacitance (Cgs). When the voltage of the Gate-Source capacitance (vgs) exceeds the threshold voltage, the MOSFET turns on unintentionally, which leads to a short circuit of the phase. This is the reason, why many papers deal with parasitic turn-on (PTO) itself and how to avoid it. In contrast to that, this article aims to use the parasitic turn-on in order to dramatically save turn-on losses.
In many applications, like traction application, which is in the focus of the paper, the maximum switching speed is determined by the maximum transient vds overvoltage. The reason for this overvoltage at turn-on is briefly explained before the measurement conditions are shown. Figure 2 shows the signals of both SiC MOSFETs in a half-bridge configuration during SiC MOSFET turn-on and Body diode turn-off.
In the following, the active switch will be the low side switch (LSS) and the complementary MOSFET the high side switch (HSS). For the hard switching turn-on, the overvoltage occurs at the HSS, where its body diode turns off the current. It can be seen, that during the dvds/dt phase (III), the vds voltage of the HSS (vds,HSS) rises above the DC-link voltage (vDC-link). The maximum vds,HSS is due to the vds voltage, which has already been taken over from the LSS (dotted) and the voltage across the commutation stray inductance due to the reverse did/dt. The reverse current consists of different effects. Especially at high temperatures and high forward did/dt, it is largely influenced by the reverse recovery of the body diode. But there is also the capacitive current due to rising vds voltage at the HSS, which is the beginning of the oscillation between the output capacitance of the HSS and the commutation stray inductance. In the case of the parasitic turn-on of the HSS, the reverse current is additionally increased due to the opening of the MOS channel.
In a light railway application, vDC-link is typically at 750 V but the DC-link voltage can go up to over 1000 V. With the usage of SiC MOSFETs with a rated voltage of Vr=1.7 kV and the assumption of a maximum of vDC-link=1.2 kV the overvoltage mustn't exceed 500 V. Therefore, the on gate resistance (Rg,on) is determined at vDC-link=1.2 kV at the maximum switching current (Isw,max) and the maximum operating temperature of 125°C. This condition is used to get the worst case reverse recovery current with the highest did/dt and thus overvoltage at the HSS. It is important to determine the off gate resistance (Rg,off) value as well, as it influences the discharge of Cgs of the HSS and thus the parasitic turn-on behavior. Hence, Rg,off was chosen to a minimum at the point of the highest transient overvoltage at the turn-off of the LSS. For the measurement, a double pulse setup with discrete 1.7 kV SiC MOSFET prototypes of about 50 A rated current (Id,r) is used. Isw,max was defined to be two times the rated current and thus 100 A. The commutation stray inductance Lσ is scaled to the get the same product Lσ⋅Id,r as a typical light railway application.
Principle of the PTO usage
SiC MOSFETs are typically turned-off with a driver voltage (vctrl) of -5 V in order to prevent PTO. But the DUT is susceptible to PTO under these conditions and thus vctrl,HSS was varied to determine, at which voltage PTO can be prevented successfully. At vctrl=-12 V there is definitely no PTO, as a further decrease of the driver voltage doesn't change the switching behavior. Rg,on was minimized to lead to 500 V overvoltage, at the conditions explained in the last section, to 73 Ω. The result is shown in solid lines in Figure 3.
When switching under the same conditions and blocking the HSS with the typical value of -5 V, the dashed curves result. Since the PTO effect also depends on the turn-off resistance, this parameter is held constant at a typical value for the application throughout all measurements. The charge flowing in reverse direction gets larger due to the temporary short circuit condition of the PTO. But in this case, the additional charge is only very small in comparison to critical PTO conditions, which may lead to failure of the device. The losses of both switches are shown in Table 1.
Due to PTO, the total turn-on losses only increase by four percent, which is not critical. But when looking at the vds,HSS curve, there is a positive effect. The PTO leads to a very small reverse did/dt of the reverse current and thus eliminates the R_(g,on) determining overvoltage. This means that Rg,on can be further decreased at vctrl=-5 V, which can be seen in Figure 4.
The dashed curves show the measurement at -5 V and 73 Ω, which was already depicted in Figure 3. The external Rg,on was reduced to 25 Ω (-.) and 0 Ω (internal Rg≈4 Ω)) (-). The lower the Rg,on, the faster the did/dt-phase, which leads to a higher reverse recovery current of the diode. Without PTO this would lead to a high reverse did/dt and thus a vds voltage above 1700 V, but in this case the PTO leads to a low reverse did/dt. Eventually, the turn-on losses reduce practically to zero at Rg,on=0 Ω as the DC-voltage is completely taken over by the stray inductance during the did/dt phase. But due to the higher reverse current, the losses of the HSS increase. The loss comparison is shown in Table 2.
It can be seen, that the losses of the LSS at Rg,on=0 Ω are negligible and the ones of the HSS increase due to the reverse current of the PTO. But overall, the losses are reduced from 26.2 mJ to 6.9 mJ. When comparing this, with the total loss of 25.1 mJ without PTO, this means the losses could be reduced by factor 3.6!
What you can additionally find in the full paper of the PCIM
This article could already show the immensely positive effect of using the parasitic turn-on effect, which was so far completely unwanted. The full paper of the PCIM also contains the measurements, where a driver voltage <-5 V is used to slightly reduce the PTO effect and thus fully exploit the possible overvoltage to further reduce the losses. Furthermore, it is shown, that the method works for a broad spectrum of operation points (different T,vdc-link and ILoad) and when considering typical threshold voltage tolerances of SiC MOSFETs. In future, a small PTO may also be used with devices, which do not show PTO at a negative driver voltage of vctrl=-5 V by increasing vctrl,HSS. Some MOSFET may even show this small PTO effect at vctrl,HSS=0 V. In addition to low turn-on losses, this would also eliminate the need of a negative driver voltage, which was mainly introduced to prevent PTO during the turn-on. Without the need for a negative driver voltage, the complexity and losses of the driver would be significantly lower.