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 Carsten Kempiak

Carsten Kempiak

Research Associate, Otto-von-Guericke-University Magdeburg

PCIM EUROPE 2021 - 2. WINNER OF YOUNG ENGINEER AWARD Power cycling under thermal overload

From Carsten Kempiak, Alexander Schiffmacher

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Highly reliable interconnect technologies are increasingly used to achieve much higher reliability or enable the device to operate at elevated temperature. These benefits, however, evolve new challenges for the qualification process.

Performing power cycling tests under thermal overload conditions to further increase the temperature swing is a promising approach to shorten the test time.
Performing power cycling tests under thermal overload conditions to further increase the temperature swing is a promising approach to shorten the test time.
(Source: ©Kadmy -


Lifetime models reveal that the lifetime of power electronic packages depends on many parameters, where the junction temperature swing ∆Tvj has by far the biggest impact. Therefore, performing power cycling tests under thermal overload conditions — beyond the specified operating range of the component — to further increase the temperature swing is a promising approach to shorten the test time. The scope of this investigation is limited to interconnects in vicinity to the chip, in particular on its top-side: When applying a short load current turn-on time it can be expected that mainly the structures close to the chip are stressed by the increased temperature swing and a highly accelerated qualification of the chip interconnects is possible without triggering a failure mechanism e.g. in the system solder layer, which still experiences a moderate temperature swing due to the thermal time constants.

Device under test

For this investigation, special engineering samples with a 650 V/200 A Si IGBT in a standard housing have been built, cf. figure 1. The bottom side of the IGBT is sintered onto a DCB while a copper bondbuffer is sintered on its top-side, carrying eight thick copper bond wires for the emitter connection. The IGBT is rated for a maximum junction temperature of 175 °C. For reference purposes, commercial modules with a similar rating (FS200R07N3E4R) and standard interconnects — thick aluminum bond wires and soldered chips — were additionally tested.

(Source: Carsten Kempiak, Alexander Schiffmacher)

Power cycling results

Exemplary power cycling results under thermal overload condition with ∆Tvj = 170 K and with a common test acceleration ∆Tvj = 90 K are shown in figure 2a for the engineering samples and in figure 2b for the reference modules, respectively. All of these power cycling tests were carried out at a medium junction temperature of Tvj,m = 120 °C and with short load pulses of ton = 0.5 s and toff = 1.5 s. In order to observe whether the underlying degradation process has changed due to the thermal overload condition, the normalized power cycling data of each DUT is plotted together:

  • For the engineering samples (figure 2a), the +5 %VCE,sat failure criterion is always met first due to a continuous increase, indicating continuously growing cracks in the top-side Al-metallisation, as intended to trigger in all test runs. Also the Rthj,c data look quite similar even considering the large difference in the number of cycles to failure Nf : Rthj,c stays roughly constant until the failure threshold is met and starts to increase afterwards, indicating additional degradations in the thermal path, which are more pronounced at higher ∆Tvj.
  • The reference modules (figure 2b), however, reveal a different behavior: At common test accelerations, overlapping degradation mechanisms on the chip’s top- and bottom-side occur, yielding an increase of Rthj,c and VCE,sat as well as of ∆Tvj, where the failure threshold of +5 % VCE,sat is met due to a typical jump in VCE,sat, indicating a bond wire lift-off. In contrast, under thermal overload conditions the degradation seems to be shifted completely to the conductive path, as indicated by the constant Rthj,c and increasing VCE,sat. Also contrary to a lower test acceleration, the failure criterion +5 % VCE,sat is met without a jump by a continuous increase, indicating a shift of the weak spot from the chip solder layer and bonds to the top-side Al-metallisation under thermal overload conditions.

(Source: Carsten Kempiak)

Obviously, the fast power cycling tests under thermal overload conditions reduce the test time drastically. In case of the engineering samples, the measured power cycling data derived for different temperature swings look qualitatively similar to figure 2a for all test runs. Therefore, the same dominating failure mechanism can be expected. Micrographic analyses confirm that the intended failure mechanism has been triggered during power cycling, as outlined in detail in the corresponding PCIM paper. In case of the reference modules, however, the failure mechanism changes under thermal overload conditions, indicating that this approach is limited to more advanced interconnect technologies.


You want to learn more about this topic? The free award winning whitepaper contains:

  • Approach for an accelerated qualification procedure,
  • description of the device under test,
  • comparative discussion of power cycling results of highly reliable engineering samples and commercial devices, and
  • a simplified lifetime model and comparison to yet published models.
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    Lifetime model

    The lifetime of the engineering samples mainly depends on the junction temperature swing and can thus be well described with the Coffin-Manson Law. The impact of Tvj,m on the lifetime can be included in the lifetime model by adding an Arrhenius-term to the Coffin-Manson law, which basically is the LESIT-model applied to the engineering samples:

    With the activation energy EA in eV, the Boltzmann-constant kB in eV/K and the medium virtual junction temperature Tvj,m in °C. For this, power cycling tests under thermal overload condition with varying Tvj,m and constant ∆Tvj = 150 K have been performed and the activation energy EA has been calculated to extend the lifetime model. The Tvj,m dependence is in turn compared to published lifetime models; the results are shown in figure 3.

    (Source: Carsten Kempiak, Alexander Schiffmacher)

    An industry wide well established rule of thumb is that an increase of 10 K halves the lifetime of electronics, which roughly fits to older IGBT power modules of the 90’s, as described by the LESIT-model; cf. figure 3b. Due to advances in the interconnect technologies, mainly of the die-attachment — as solder degradation reveals a much more pronounced Tvj,m dependence than bond wire failures — this rule of thumb does not fit to more modern IGBT power modules of 2000’s and later, as described by the CIPS08-model. Their lifetime is much less affected by higher temperatures. Further innovations in the die-attachment like silver-sintering yield even more reduction in the Tvj,m dependence of the lifetime as described by the SKiM63-model and is also confirmed by this investigation. This can be explained by a reduction of the stiffness of silver-sintered compounds at higher temperatures, yielding less plastic strain. This property, however, is amongst others strongly affected by the sintering and process parameters, which underlines the importance of a suitable qualification. This is efficiently supported by power cycling under thermal overload as described, allowing for a rapid product and process optimization. The failure analyses, a more detailed description and discussion of this investigation as well as references can be found in the corresponding PCIM paper ”Accelerated Qualification of Highly Reliable Chip Interconnect Technology by Power Cycling under Thermal Overload”.

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    This IGF research project with the no. 19910 BG of the research associations FVA (Forschungsvereinigung Antriebstechnik e.V.) was funded on the basis of a decision of the German Bundestag, represented by the Federal Ministry of Economy and Energy (BMWi) via AiF within the framework of the program for the promotion of joint industrial research and development (IGF).

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