BASIC KNOWLEDGE - RISC-V RISC-V: what is it all about?
UC Berkeley developed the RISC-V instruction set as a CPU lingua franca for computer chips; an architecture used by all chipmakers and owned by nonei. Here, we look at RISC-V and some of the technology and applications it has facilitated.
The Eighties battle for processor dominance locked us into proprietary and expensive models - and, today, as demand for many types of processors is exploding, proprietary standards continue to dictate processor architecture, according to RISC-V Internationalii.
As a response to this, RISC-V has been developed as a free and open Instruction Set Architecture (ISA); it enables processor, hardware and software innovation through open collaboration while disrupting traditional microprocessor business models. Developers are no longer limited to traditional proprietary architectures. The model also eliminates financial hurdles such as licensing, royalty fees and development costs.
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RISC-V’s open standard instruction set architecture is based on established Reduced Instruction Set Computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open-source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware. Open-source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchainsiii.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, and a design that is architecturally neutral. It places most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. It is variable-width and extensible so that more encoding bits can always be added.
It supports three word-widths - 32, 64, and 128 bits - and a variety of subsets. The definitions of each subset vary slightly for the three word-widths. The subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19-inch rack-mounted parallel computers.
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The instruction set space for the 128-bit stretched version of the ISA was reserved because 60 years of industry experience has shown that the most unrecoverable error in instruction set design is a lack of memory address space. As of 2016, the 128-bit ISA remains undefined intentionally, because there is yet so little practical experience with such large memory systems. There are proposals to implement variable-width instructions up to 864 bits long, 27 times the usual length. As of June 2019, version 2.2 of the user-space ISA and version 1.11 of the privileged ISA are frozen, permitting software and hardware development to proceed. The user-space ISA, now renamed the Unprivileged ISA, was updated, ratified and frozen as version 20191213. A debug specification is available as a draft, version 0.13.2.
History and community
The project began in 2010 at the University of California, Berkeley along with many volunteer contributors not affiliated with the university. The RISC-V instruction set was developed in the University’s Parallel Computing Laboratory (Par Lab); this was a five-year project to advance parallel computing funded by Intel, Microsoft, other industrial sources, and California State. The Chisel hardware construction language, used to design many RISC-V processors, was also developed in the Par Lab.
Unlike other academic designs which are typically optimized only for simplicity of exposition, the designers intended that the RISC-V instruction set be useable for practical computers. Today, the RISC-V community is overseen by RISC-V International - a global non-profit association based in Switzerland. Founded in 2015 as the RISC-V Foundation with 29 members, RISC-V is now a global organization with over 750 members in more than 50 countriesiv.
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No patents related to RISC-V have been filed, as the RISC-V ISA itself does not represent any new technology. The RISC-V ISA is based on computer architecture ideas that date back at least 40 years. RISC processor implementations—including some based on other open ISA standards— are widely available from various vendors worldwidev.
RISC-V International does not manage or make available any open-source RISC-V implementations, only the standard specifications. RISC-V software is managed by the respective open-source software projects.
By fueling innovation in chip design tools and software, RISC-V allows custom microprocessors to reach the market far more rapidly than previously possible. With its modular approach, RISC-V allows designers to take just those pieces and parts that are required for their specific design; this approach is being adopted in industry, from embedded applications to enterprise projects.
Areas include mobile and wireless applications, where dozens of processors reside on a single device, as well as automotive, where safety and reliability are paramount. Growth also continues in IoT applications, which were early adopters; additionally, it persists in existing workloads such as memory or GPU controllers.
A recent microprocessor design from Micro Magic Inc.vi, a Silicon Valley intellectual property designer for chips, provides one example of the technology breakthroughs being facilitated by RISC-V. The prototype chip has a clock speed of 5 gigahertz, well above a recent, top-of-the-line Intel Xeon server chip, E7, running at 3.2 gigahertz. Yet the novel RISC-V chip burns just 1 watt of power at 1.1 volts, less than one percent of the power demanded by the Intel Xeon.
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The breakthrough lies in the way the CPU and memory interact. Micro Magic’s founders had previously patented a SRAM computer memory chip, which was the fastest such chip ever developed. The RISC-V prototype eliminates a bottleneck that can exist with fast memory and slower chipsvii.
The contribution of RISC-V to open source and open standards
Advances in software and hardware standardization through global collaboration and consensus, as well as open source development and delivery of software and hardware design, has accelerated technical progress at an unprecedented global scale. RISC-V Internationalviii is focused on the release of RISC-V to the open community for both standardization and ongoing improvement through open collaboration.
Without collaboration and open access to the RISC-V ISA and open extensions, the community risks fragmentation, forking, and the establishment of multiple standards. Such multiplicity diminishes the strategic value and longevity of the architecture, as technology providers rely on global standards to advance partnerships and supply chains as well as participate in global markets for their products and services.
i & vii RISC-V, the Linux of the chip world, is starting to produce technological breakthroughs
ii & iv About RISC-V
iii RISC-V Wikipedia
v & viii History of RISC-V
vi Micro Magic, Inc.