Towards Digital Twins of Power Electronic Switching Cells

This research aims to identify PCB layout design parameters leading to an improved layout design with respect to low switching losses and low electromagnetic interference. A digital twin of switching cells containing discrete silicon carbide power devices was developed and verified by double-pulse measurements. The results identify and quantify the non-negligible influence of the layout parasitic capacitances on the optimization of switching losses. The observed modeling challenges point towards the need for more accurate electromagnetic modeling techniques for power electronics applications and for standardization of SiC power MOSFET Spice models. With the optimized layout based on the developed more precise modeling approach, switching losses have been reduced by more than 7 %.

 

This whitepaper demonstrates:

• A state-of-the-art electromagnetic tool and Spice-based device models for virtual prototyping of Power Electronic Switching Cell layouts
• The comparison between a 2-D FEM device model and Spice-based behavioral models - pointing to the necessity for standardization of Spice compact models
• A virtual prototype of Power Electronic Switching Cell layout used to re-design the PCB layout for lower switching losses
• For fast switching devices, not only parasitic layout inductances but also PCB parasitic capacitances have to be minimized!