## POWER DELIVERYWhat’s the most efficient way to deliver electrical power?

From Nigel Charig

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Whether a power delivery network comprises pylons in a national grid, or copper tracks on a printed circuit board, it can operate more efficiently at higher voltages.This article explains why this is so, and then shows how power delivery efficiency is an increasingly important issue for today’s power-hungry devices.

Our hi-tech lives owe much to power delivery networks, or PDNs. PDNs transport electrical energy from a power source to the load that needs it – and a PDN path could be a power plane on a computer motherboard, the cable harness in an electric vehicle, or the pylons and cables of the National Grid.
Despite their extravagantly varying levels of scale, all these PDNs have one thing in common; the higher the voltage they operate at, the more efficiently they run.

### Voltage, current, resistance… and power

If we apply a voltage V across a simple resistive load of resistance R ohms (Ω) as shown in Fig.1, then a current I amps will flow through it according to the equation:

V = I x R (1)

It’s also true that the load will consume power in watts according to the equation

W = V x I (2)

If we substitute for V in equation (2) we get

W = (I x R) x I

W = I2R (3)

While Fig.1 is a simple illustration of the relationship between V, R and I, Fig.2 is a representation of a power delivery network on, say, a computer motherboard. The Load could be a CPU or graphics processor chip. RPDN represents the fact that, in practice, a PDN must always have some resistance, no matter how small.

From now on, we can let the figures do the talking. Suppose the load draws 96W. According to equation (2) (W = V x I) this could be satisfied equally well by 12V at 8A, or 48V at 2A. Meanwhile, let’s assume that RPDN = 1Ω.

However, simply applying 12V or 48V across the Fig. 2 circuit’s input terminals would not suffice. There would be a voltage drop, and associated losses, as the current flowed through RPDN of 1Ω. At 12V/8A, these losses are W = I2R or 64W. At 48V/2A, losses drop to just 4W!

If we imagine these figures magnified by a factor of 10 or more for today’s more powerful processors, or to even higher levels for other applications, the efficiency-saving benefits of operating PDNs at higher voltages soon become very clear.

### An increasingly critical issue

The above example discusses a hypothetical situation with fairly modest power levels. The reality, however, can be very different. As we build ever more functionality and performance into our electrical and electronic devices, their power demand increases incessantly and sometimes dramatically.

Vicor, for example, has noted that peak currents for CPU and graphics processor devices, which were typically around 700A in 2015, can now reach 1500A. To some extent this can be sustained by delivering power to and across the processor printed circuit boards (PCBs) at 48V rather than the earlier norm of 12V, but a problem remains; the point of load (PoL) processor device normally operates at a much lower voltage.

Previously, this problem could be solved by delivering power at 48V to a DC-DC converter mounted next to the PoL. The converter would then provide a low voltage, high current output, which had only to travel a short distance across the PCB, so I2R losses were manageable. However, as current levels climb towards 1000A continuous, the losses become an issue. If the path from the DC-DC converter to the PoL has a resistance of 400 microhms, then I2R losses in the board can amount to 400W; half the delivered power is being dissipated as heat in the motherboard and interconnections.

Vicor has developed a couple of solutions to this, which minimise or eliminate the distance between the converter and PoL, or ‘last inch’ as they call it. They factorize the power conversion process by breaking it down into a regulation and a current transformation stage. The regulator, with its 48V output, can be distant from the point of load, while the current transformer (or current multiplier), with its high-current output, is located on the processor substrate or even in the processor package. This technique, known as Lateral Power Delivery, can reduce the power delivery path resistance to 50 microhms. This will improve efficiency to 93.75 percent, and reduce I2R losses to 50W.

If even better efficiency is required, Vertical Power Delivery can be used. This uses a geared current multiplier (GCM), which has not only current multiplication but also bypass capacitance. It is typically positioned directly underneath the processor chip, along with a gearbox or interconnect layer that maps the GCM output connections to the processor power inputs. This allows most of the GCM’s current output to be transferred directly upwards to the processor. Efficiency can reach 99.4 percent at 1000A, with losses reduced to 5W.